Plenary Talks


November 6 (Tuesday)

Circuit Design in Nano-Scale CMOS Technologies


  • Dr. Kevin Zhang
  • VP, Business Development, TSMC, Taiwan




  • Date: November 6 (Tuesday)
  • Time: 08:50 - 09:35
  • Room: Far Eastern Grand Ballroom A+B, B2F

Abstract:

The relentless pursuit of Moore's law by semiconductor industry has led the feature size of CMOS transistor well into nano-scale regime. Deeply scaled technologies have created many new challenges for circuit design, e.g., device variation and voltage head-room. In this presentation, an overview of today's semiconductor technology landscape will be presented first, including major innovations that have kept the scaling continue. Then the focus of this talk will be on how to address the scaling challenges with novel circuit design techniques, covering key circuit design areas, digital, memory, analog, and mixed signals. A number of real design examples will be used to illustrate the new design concepts that are proven to be effective in helping the scaling. A central theme throughout the presentation will be around the technology-design optimization in order to continue to harvest the benefits of technology scaling.


Biography:

Dr. Kevin Zhang currently serves as Vice President of Business Development. Prior to this role, Dr. Zhang served as Vice President of Design and Technology Platform. Before joining TSMC in November 2016, Dr. Zhang was Vice President of Technology and Manufacturing Group and Director of Circuit Technology at Intel, where he was responsible to the development of process design rules, circuit & device modeling, digital libraries, key analog and mixed-signal circuits. He led the development of embedded memory technologies from 90nm to 10nm at Intel. He was also responsible to the design and validation of lead vehicles for process technology development at Intel. Dr. Zhang was elected as Intel Fellow in 2005 and led his teams to win 5 Intel Achievement Awards, the highest technical accomplishments at the company.

Dr. Zhang has published more than 80 papers at international conferences and in technical journals and is the editor of Embedded Memory for Nano-Scale VLSIs, published by Springer in 2009. He holds 55 U.S. patents in the field of integrated circuit technology. Dr. Zhang was the 2016 International Solid-State Circuit Conference (ISSCC) Program chair and serves on IEEE VLSI Executive Committee. He is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE). He received his bachelor's degree from Tsinghua University in Beijing and his Ph.D. from Duke University, both in electrical engineering.





Open the New World of 5G


  • Mr. Seizo ONOE
  • CTA, NTT DOCOMO & President, DOCOMO Tech., Japan




  • Date: November 6 (Tuesday)
  • Time: 09:40 - 10:25
  • Room: Far Eastern Grand Ballroom A+B, B2F

Abstract:

5G is stimulating people’s imagination and expectations for a new world that it may bring about by the year 2020. 5G is aimed at meeting a wide range of requirements such as further enhanced mobile broadband, massive connections and reliable critical communications with low latency. Furthermore, it is highly expected to invent new business models and ecosystems across the industries.

In the presentation, first the history of mobile communications is reviewed to predict the future. Next, what 5G would create is discussed, which is followed by the discussion on 5G economics. Some concerns about the economics of 5G deployment are seen here and there because people tend to believe 5G would need a huge number of small cells due to limited coverage caused by higher spectrum bands. In the past, more than 30 years ago, no one believed the realization of the 2GHz cellular system. Mobile technologies have achieved many things that were once thought impossible, driven by semiconductor technology evolution. In the future, cost-effective 5G systems with millimeter waves must be realized by further evolved mobile and semiconductor technologies. Lastly, predictions are introduced being derived from the two laws that the speaker has defined. One is the law of previous generations’ boom just before the next and the other is the law of great success only in even-numbered generations.


Biography:

Seizo ONOE became Chief Technology Architect of NTT DOCOMO, INC in June 2017 after his 5 years tenure as Chief Technology Officer, while retaining the position of President of DOCOMO Technology, Inc. since June 2015. Prior to his current position, he was Chief Technology Officer and Executive Vice President and a Member of the Board of Directors of NTT DOCOMO from June 2012. Mr. Onoe became a Senior Vice President and Managing Director of the R&D Strategy Department in June 2008. He was a Vice President and took the position of Managing Director of departments in charge of Radio Access Network development from July 2002 to June 2008.

He has been responsible for leading initiatives in the research and development of the analog cellular system (1G), the digital cellular system (2G), W-CDMA/ HSPA (3G), LTE, LTE-Advanced (4G) and 5G. He has been working on the research and development of radio access networks, core networks, consumer devices and services. He has worked for NTT and NTT DOCOMO since 1982, acquiring more than 30 years of experience. Mr. Onoe has a master’s degree in electronics from the Kyoto University Graduate School of Engineering.




November 7 (Wednesday)

Practical Challenges in Supporting Functions in Memory


  • Dr. Nam Sung Kim
  • SVP, Memory Division, Samsung, Korea



  • Date: November 7 (Wednesday)
  • Time: 08:30 - 09:15
  • Room: Far Eastern Grand Ballroom A+B, B2F

Abstract:

As data transfers between processors and memory become the performance and energy-efficiency bottleneck, supporting Functions in Memory (FIM) has emerged as an attractive computing paradigm. This plenary talk covers various challenges in making FIM practical especially for industry adoption. Specifically, it will first give insight on why it is hard to offer higher bandwidth and lower latency for processors/accelerators in memory unlike most researchers assume. Second, it will describe various technical challenges to make FIM synergistically work with existing computers. Lastly, it will discuss future directions for the research community to make FIM more practical.


Biography:

Dr. Nam Sung Kim has worked on interdisciplinary research topics incorporating device, circuit, architecture, and system software for energy-efficient computing systems. Before he joined Samsung as a Sr. VP, he was a tenured faculty member of the University of Illinois, Urbana-Champaign and the University of Wisconsin, Madison. He received BS and Ph.D. degrees from KAIST and the University of Michigan, Ann Arbor, respectively. He has published more than 180 refereed articles to highly-selective conferences and journals in the field of digital circuit, processor architecture, and computer-aided design. The top three most frequently cited papers have more than 3500 citations and the total number of citations of all his papers exceeds 8400. He was a recipient of the ACM/IEEE International Symposium on Microarchitecture (MICRO) Best Paper Award, ACM/IEEE Most Influential International Symposium on Computer Architecture (ISCA) Paper Award, IEEE Micro Top Picks. He is a member of IEEE International Symposium on High-Performance Computer Architecture (HPCA) Hall of Fame and MICRO Hall of Fame.





AI Drive Domain Specific Processors


  • Dr. Yi Kang
  • Chief Scientist & SVP, UNISOC, China (Tsinghua Unigroup)




  • Date: November 7 (Wednesday)
  • Time: 09:20 - 10:05
  • Room: Far Eastern Grand Ballroom A+B, B2F

Abstract:

Today most of hardware solutions for Artificial Intelligence (AI) use one of the following approaches, general purpose CPU GPU, or ASIC. While CPU and ASIC represent two extremes in term of efficiency and flexibility, GPU is more widely used and is a good compromise of different approaches. Domain Specific Processor or Domain Processor was proposed in recent years to meet with challenge of AI. Actually GPU can be considered as an example of Domain Processor, it is a PE mesh that is good for pixel based operations which consists of multiply, add that can be carried out in a massive parallel way. As AI evolves very dynamically and fast in recent year and perceivably in future, it calls for new type of Domain Processors. Currently most of AI hardware solutions are aiming at speeding up computations in Convolution Neural Network (CNN) where more than 80% of its computation is consisted of a series of dot products. ASIC type of solutions are efficient at performing parallel multiply-accumulate (MAC) operations in CNN but they are not fit for other type operations. There are other types of operations in CNN, for example, floating point division, permutations, operations for pruning sparse matrix etc. According to Amdahl Law, these operations need to be speed up otherwise total speedup is limited. Moreover, more and more new AI algorithms are developed in which percentage of MAC operations is less dominant compared to CNN. In this talk it is described that Domain Processor will be a trend in AI hardware development . The reason is that Domain Processor can provide enough horse power to meet AI’s hunger for computation while provide good flexibility and programming ability at the same time for AI’s evolution along its course. Compared to general purpose CPU, Domain Processor has better power consumption and better performance; Compared to ASIC, Domain Processor is more flexible and is equivalent in performance. In the talk Vector Processing is presented as an important feature for AI Domain Processor. Vector Processing is good at computation intensive load such as sparse matrix operations, permutations, general type of floating point operations and Vector Processor usually can provide enough memory bandwidth to support large number of computations, thus Vector Processor is good for AI applications. Recent development for AI on general purpose CPU architecture such as ARM suggests this point too. Some of important features for AI Domain Processor are also mentioned in the talk.


Biography:

Dr. Yi Kang is currently Chief Scientist and Senior Vice President at UNISOC (formally known as Spreadtrum), in charge of research and development for advanced technologies including 5G, AI and CPU. He joined in Spreadtrum in 2003 and was the overall project leader for many key IC development projects including the industry’s first TD-SCDMA baseband chip, China’s first mobile CPU core, company’s first 4G multimode baseband chip and first mobile TV chip etc. Before joining Spreadtrum, Dr. Kang has more than 10 years engineering development and management experience with a few high-tech companies in field of high performance microprocessor, DSP, network security in US.

Dr. Yi Kang has published 14 papers in journals and conferences, he has 40 US and China patents as co-inventor. His current research interest is in wireless communication, microprocessor architecture and high speed digital circuit implementation. He is a member of China IMT-2020 Working Group that is a major 5G Alliance in China with experts from industry, universities and government agencies, he is aslo a director of China Communication Standardization Association. Dr. Yi Kang received his BE and ME both from Tsinghua University in Beijing in Electronic Engineering, and PhD from University of Illinois at Urbana-Champaign in Computer Science.





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