Tutorials


November 5 (Monday)

Tutorial 1: When SAR Meets ΔΣ - A Tale of Two ADC Architectures -


  • Nan Sun
  • University of Texas at Austin, USA



  • Date: November 5 (Monday)
  • Time: 09:00 - 10:30
  • Room: South+West+East Gate, B1F

Abstract:

SAR is widely used for medium resolution applications due to its simplicity, scaling compatibility, and low-power consumption. However, its power efficiency degrades as the resolution increases due to its tight requirement on the comparator noise and the exponentially growing capacitor DAC array. By contrast, ΔΣ ADC is a popular architecture for high-resolution applications. Taking advantage of noise shaping, it can achieve high resolution with a low-resolution quantizer and DAC. However, it typically requires the use of op-amps that are power hungry and scaling unfriendly.

This tutorial will review latest hybrid ADCs that aim to combine the merits of SAR and ΔΣ while simultaneously obviating their drawbacks. After presenting a high-level overview of published works, we will take a deep dive into two interesting noise-shaping SAR ADC architectures. The first one uses fully passive switched-capacitor filter to achieve 2nd-order noise shaping. It is fully dynamic and can be easily duty cycled. In addition, it is robust and calibration free. Thus, it is well suited for low-power sensor applications. The second one adopts an error-feedback structure, which simplifies the filter design. It consumes very low power by using a dynamic amplifier and address its process, voltage, and temperature (PVT) sensitivity via a fast-convergence background calibration loop.


Biography:

Nan Sun is Associate Professor at the University of Texas at Austin. He received the B.S. degree from Tsinghua University, China in 2006, where he ranked top in Department of Electronic Engineering. He received the Ph.D. degree from Harvard University in 2010. Dr. Sun received the NSF Career Award in 2013 and Jack Kilby Research Award from UT Austin in both 2015 and 2016. He won Harvard Teaching Award from 2008 to 2010. He serves in the TPC of IEEE Custom Integrated Circuits Conference and Asian Solid-State Circuit Conference. He is Associate Editor for IEEE Transactions on Circuits and Systems – I: Regular Papers, and Guest Editor for IEEE Journal of Solid-State Circuits. He is currently taking sabbatical at Tsinghua University until summer 2019.





Tutorial 2: Wireless ECG Acquisition and Cardiac Stimulation SOCs for Body Sensor Networks


  • Shuenn-Yuh Lee
  • National Cheng Kung University, Taiwan



  • Date: November 5 (Monday)
  • Time: 10:50 - 12:20
  • Room: South+West+East Gate, B1F

Abstract:

There are several medical devices are made to monitor their heart to avert the heart diseases. Moreover, body sensor networks (BSNs) based applications or wearable devices have become more acceptable to the people for monitoring the real-time health information, such as the electrocardiogram (ECG). In order to enhance the portability of BSNs, a low-power wireless ECG acquisition system on a chip (SOC) stuck on the body is required. In this tutorial, a bio-signal acquisition system with the features of low power consumption, wireless transmission, and the on-time monitoring will be presented. Moreover, some researches have been reported that it is efficient to electrically generate neural action potential to control dysfunctional organs. Therefore, the telemetry integrated circuits will be required because they can provide coupling power and are able to transmit or receive data to or from according to implantable body sensor network. In this tutorial, a closed-loop implantable micro-stimulator system on chip (IMSoC), which possesses the sensing of a physiological signal, micro-stimulation, and wireless data/command transmission, will be also presented.


Biography:

Shuenn-Yuh Lee received the B.S. degree from the National Taiwan Ocean University, Keelung, Taiwan, in 1988, and the M.S. and Ph.D. degrees from the National Cheng Kung University, Tainan, Taiwan, in 1994 and 1999, respectively. He is currently a Professor at the Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan. From 2013 to 2016, he serves as the Chairman of IEEE Solid-State Circuits Society Tainan Chapter. From 2016 to 2017, he serves as the Vice Chairman of IEEE Tainan Section. He is the Associate Editor of IEEE Transaction on Biomedical Circuits and Systems from 2016-2019. His present research activities involve the design of analog and mixed-signal integrated circuits, biomedical circuits and systems, low-power and low-voltage analog circuits, and RF front-end integrated circuits for wireless communications.





Tutorial 3: Terahertz CMOS Technology for Beyond 5G


  • Minoru Fujishima
  • Hiroshima University, Japan



  • Date: November 5 (Monday)
  • Time: 13:40 - 15:10
  • Room: South+West+East Gate, B1F

Abstract:

The fifth generation (5G) is about to begin in 2020. New applications are expected in 5G where data rate of 10 Gb/s and low delay of 1 ms are realized. Meanwhile, discussion on "Beyond 5G" after 10 years is beginning to start, since the mobile generation has evolved every decade.

The need for high-speed communication continues in the future since the data handled over the Internet is exponentially increasing. How can we realize the target communication speed of 100 Gb/s in Beyond 5G? One powerful candidate is a new communication technology using the 300-GHz band which is one of the terahertz bands. In this presentation, firstly, the evolution of communication speed is introduced, and the reason why wireless communication has dramatically increased the data rate will be discussed. Then, after the superiority of the 300-GHz band usable for wireless communication is introduced, CMOS technology for realizing the 300-GHz-band wireless communication is explained. Finally, how the world changes with beyond 5G using terahertz communication will be discussed.


Biography:

Minoru Fujishima received the B.E., M.E. and Ph.D degrees in Electronics Engineering from the University of Tokyo, Japan in 1988, 1990 and 1993, respectively. He joined faculty of the University of Tokyo in 1988 as a research associate, and was an associate professor of the School of Frontier Sciences, University of Tokyo since 1999. He was a visiting professor at the ESAT-MICAS laboratory, Katholieke, Universiteit Leuven, Belgium, from 1998 to 2000. Since 2009, he has been a professor of the Graduate School of Advanced Sciences of Matter, Hiroshima University.

He studied design and modeling of CMOS and BiCMOS circuits, nonlinear circuits, single-electron circuits, and quantum-computing circuits. His current research interests are in the designs of low-power millimeter- and short-millimeter-wave wireless CMOS circuits. He coauthored more than 50 journal papers and 120 conference papers. He served as a distinguished lecturer in IEEE solid-state circuits society from 2011 to 2012.





Tutorial 4: Memory System for Next Generation AI


  • Kyomin Sohn
  • Samsung Electronics, Korea




  • Date: November 5 (Monday)
  • Time: 15:30 - 17:00
  • Room: South+West+East Gate, B1F

Abstract:

Now, it is the era of deep learning and AI. Among various approaches to accelerate neural network calculation, HBM (high bandwidth memory) DRAM is one of key components in a state-of-the-art accelerators.

Basically, HBM DRAM shows unparalleled bandwidth like 1TB/s in a small SiP (system in package). To provide this huge bandwidth, there are many challenges like power density, thermal dissipation, testability and reliability from stacking and 2.5D configuration.

In this tutorial, the reasons for using HBM in accelerators are explained in detail, and the key schemes of HBM and difficulties of developing and using HBM will be discussed. Furthermore, the requirement of memory system for next generation AI and the promising features including near data processing are also touched.


Biography:

Kyomin Sohn received the B.S. and M.S. degrees in Electrical Engineering in 1994 and 1996, respectively, from Yonsei University, Seoul. From 1996 to 2003, he was with Samsung Electronics, Korea, involved in SRAM Design Team. He designed various kinds of high-speed SRAM devices.

He received the Ph.D. degree in EECS in 2007 from KAIST, Daejeon, Korea. He rejoined Samsung Electronics in 2007, where he has been involved in DRAM Design Team. He is a Master (Technical VP) in Samsung and he is responsible for development of HBM DRAM and Future Technology.

His interests include the next generation 3D-DRAM, robust memory design, and processing-in-memory for AI applications. Since 2012, he has currently served as a Technical Program Committee member of Symposium on VLSI Circuits.





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